HDMI 2.1¶

LattePanda Mu x86 compute module derives up to 3 HDMI outputs from the DDIB, TCP0, and TCP1 interfaces, supports up to 4K @ 60Hz.

Interface Configuration¶

• HDMI signals(operating in TMDS mode) can only be configured from DDIB, TCP0, or TCP1.

• The default BIOS enables DDIB and TCP0 as HDMI.

  To configure TCP1 as HDMI(TMDS mode), a specific BIOS firmware must be flashed. Dynamic switching via the BIOS menu is not supported.

Design Guidelines¶

Pin Definition¶

AC Coupling & Pull-down Bias¶

Intel's reference design requires a specific AC Coupling + Pull-down Bias topology.

• AC Coupling: A 100nF (0.1uF) capacitor must be placed in series on all four TMDS differential pairs. 0402 or smaller package is recommended to minimize parasitics.
• Pull-down Bias: After the capacitor (connector side), each TMDS signal line must be pulled down to GND via a 470Ω resistor.

• Switch Control: The ground connection of all 470Ω resistors should be gathered and controlled by an NMOS. The NMOS turns ON (enabling the pull-downs) ONLY when the system is in the Working (S0) state.

  

Polarity Check¶

HDMI TMDS differential pairs do not support polarity inversion.

Strict polarity matching must be implemented on the carrier board. Ensure that Positive (+) maps to Positive (+) and Negative (-) maps to Negative (-), as illustrated in the figure below.

+---------------------+                            +---------------------+
|  Compute Module     |                            |   HDMI Connector    |
|                     |      Carrier Board         |                     |
|  [TMDS_DATA_P] (+)  | O========================O |  (+) [Pin X]        |
|                     |                            |                     |
|  [TMDS_DATA_N] (-)  | O========================O |  (-) [Pin Y]        |
|                     |                            |                     |
+---------------------+                            +---------------------+
          ^                                                   ^
          |                                                   |
          +----------- STRICT 1:1 MAPPING REQUIRED -----------+
                       (Do NOT Swap P & N Signals)

Level Shifter¶

• DDC (I2C) and HPD signals from compute module are 3.3V.
• HDMI standard requires 5V logic levels.
• Direct connection is prohibited. A level shifting circuit (using NMOS or dedicated chips) must be implemented on the carrier board.

No AUX Signal¶

When operating in TMDS mode, the AUX signals are unused, so they should be left not connected.

For example, when DDIB is operating in TMDS mode, the following pins should be NC.

Pin 191: DDIB_AUX_N 
Pin 193: DDIB_AUX_P

ESD Protection¶

Since HDMI ports are subject to frequent hot-plugging, they are vulnerable to Electrostatic Discharge (ESD). And TMDS signals are extremely sensitive to capacitance. So Ultra-low capacitance ESD protection diodes are mandatory.

Layout Guidelines¶

Spacing & Crosstalk¶

• Trace Type: Microstrip Differential Pair

• Recommended Pair-to-Pair Spacing: ≥ 5W (where W is trace width).

  To ensure signal integrity for HDMI 2.1 (4K@60Hz) , a spacing of at least 5W is required to strictly minimize crosstalk.

• Recommended General Spacing: Maintain at least 5W spacing between high-speed TMDS pairs and other signals (DDC, HPD, Power).

• More details in High-Speed Interface Layout Guidelines

Differential Pair Net Length¶

The follow tables list the LattePanda Mu compute module track-length for the DDIB, TCP0 and TCP1 interfaces.